4021 - Static Shift Register

The 4021 is an 8-stage static shift register, featuring parallel input/serial output. It supports parallel/serial control, enabling data to be shifted serially with the clock or jammed asynchronously. Housed in a 16-pin DIP package, it offers high noise immunity, ESD protection, and low power dissipation, making it compatible with TTL, CMOS, and NMOS devices.

CD4021BE Static Shift Register in PDIP-16 package
Fig.: CD4021BE Static Shift Register in PDIP-16 package

Specifications/Features

Input/Output Parallel Input/Serial Output
Supply Voltage (VDD) 3V to 18V
Operating Temperature -55°C to 125°C
Clock Frequency (Max) 8.5 MHz (at VDD = 15V)
Power Dissipation 500 mW
Input Capacitance 5 pF (typical)

📄 CD4021B datasheet (3978 kB)

Connections

Terminal diagram of the 4021
Fig.: Terminal diagram of the 4021
Pin No Pin Name Description
1 P8 Parallel Input 8 of Shift Register
2 Q6 The output of Shift Register 6
3 Q8 The output of Shift Register 8
4 PI-4 Parallel Input 4 of Shift Register
5 PI-3 Parallel Input 3 of Shift Register
6 PI-2 Parallel Input 2 of Shift Register
7 PI-1 Parallel Input 1 of Shift Register
8 GND Ground
9 Parallel/Serial Input Latch Input
10 Clock Clock Signal Input
11 Serial In Serial Input
12 Q7 The output of Shift Register 7
13 PI-5 Parallel Input 5 of Shift Register
14 PI-6 Parallel Input 6 of Shift Register
15 PI-7 Parallel Input 7 of Shift Register
16 VCC Drain Supply

Further information

Last edited by Christian Grieger on 2025-05-10
←
X
  1. [top]
  2. Specifications/Features
  3. Connections
  4. Further information